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Session Track: General
Light Lunch Buffet
  • Speaker:  
Time: Monday, May 07, 12:00 - 13:30, Room: Conference Area
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Session Description: Light Lunch Buffet

Session Track: Academic
[AC01] Updated Cadence 2018 Portfolio Available for European Academics via Europractice
  • Speaker: Bryony Howard, Science and Technology Facilities Council  
Time: Monday, May 07, 13:30 - 14:00, Room: Pilsensee
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Session Description: Updated Cadence 2018 Portfolio Available for European Academics via Europractice


Bryony Howard Bio:
Session Track: Automotive and IP Solutions
[ASIP01] Addressing IP Management and Traceability Challenges for ISO 26262
  • Speaker: Michael Munsey, Vice President Business Development and Strategic Accounts, Methodics 
Time: Monday, May 07, 13:30 - 14:00, Room: Schliersee
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Session Description: The escalating use and reuse of IP in complex IC design continues to challenge design teams from a complexity management standpoint. IP-driven design also adds more pressure when conforming to industry standards that chip makers must comply with. ISO 26262, the automotive functional safety standard, is a requirement in that sector, and necessitates strict practices with regard to how IP is selected, qualified, used and documented – regardless of source and throughout the entire life cycle. The challenges get compounded by remote design teams, constant versioning of IP, and multiple archiving scenarios. This session will provide an overview of an IP lifecycle and workspace management solution to ensure that no matter where designers are located or where the IP originated, teams have full traceability - from requirements through to the IP used in the design and its resulting verification information - as well as full visibility into the IP available to them and access to all related data. We will present how the Percipient Platform integrates with the Cadence environment, making designs more efficient and predictable with higher quality of results. By integrating with requirements management systems, companies now have traceability required by ISO26262 from concept throughout design and delivery, all the way down to the individual IP used within semiconductor development.


Michael Munsey Bio: Michael Munsey has over 25 years experience in Engineering Design Automation and Semiconductor Companies. Prior to joining Methodics, Michael was Senior Director of Strategy and Product Marketing for semiconductors, software life cycle management, and IoT at Dassault Systemes. Along with strategic initiatives, he was responsible for business development, partnerships, and cross-industry initiatives such as automotive electronics, and M&A in the above areas. Michael began his career with IBM as an ASIC designer before making the move over to EDA where he has held various senior and executive-level positions in marketing, sales, and business development. He was a member of the founding teams for Sente and Silicon Dimensions, and also worked for established companies including Cadence, VIEWLogic, and Tanner EDA. Michael received his BSEE from Tufts University.
Session Track: Custom
[CUS01] Lifetime Verification by Circuit Level Aging Simulations
  • Speaker: Roland Jancke, Head of Department Design Methodology, Fraunhofer Institute for Integrated Circuits IIS 
Time: Monday, May 07, 13:30 - 14:00, Room: Ammersee I
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Session Description: More and more applications of integrated circuits are safety-critical or require particularly long lifetimes, for instance in automotive, medical, or industrial electronics. To take this requirement into account, the long-term behavior of an integrated circuit or an IP block can be verified by circuit-level aging simulations. These analyses are based on (a) application scenarios for the product and (b) aging models for the used semiconductor devices. Within the European project ADMONT, aging models were set up for two devices in X-FABs XU035 technology. The models cover negative bias temperature instability (NBTI) of a PFET as well as hot carrier injection of the PFET and an NFET. They were set up to represent the measured degradation in multiple electrical characteristics: VTH, IDLIN, IDSAT, and GMAX. We applied the Cadence URI API to implement the aging models to be available in simulations with Cadence RelXpert as well as Cadence Spectre native. We ran RelXpert simulations to investigate the reliability of a piezo-electric driver circuit, which is required to provide a long lifetime at a high accuracy due to its target applications. To achieve the functionality, transistors of the XU035 technology in multiple voltage classes were used. The RelXpert simulations verified a sufficient circuit reliability.


Roland Jancke Bio: Degree "Dipl-Ing." from Technical University Dresden, Since then with Fraunhofer Institute for Integrated Circuits IIS, Design Automation Division, now Division Engineering of Adaptive Systems; Since 2011 Group Manager Reliability and Test, Since 2016 Head of Department Design Methodology
Session Track: Full-Flow Digital Design and Signoff
[DSG01] So How Can the HLS Flow Help You Cut TTM?
  • Speaker: Dror Constantinis, Staff Application Engineer, Cadence 
Time: Monday, May 07, 13:30 - 14:00, Room: Ammersee II
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Session Description: Recently, more and more logic designs are being crafted with high-level synthesis flow. This is a significant change- from detailed coding using HDLs to code in a higher abstraction using SystemC. This paper will drill down to the technical details of the flow and how does it help to shorten the time from spec to high quality RTL. We will ask and answer the questions – What raises the productivity of HLS designs as compared to RTL design? How come it reduced TTM significantly, without a hit in the QoR?


Dror Constantinis Bio:
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